ROD development with final ROD motherboard
Introduction
The TileCal
ROD system final motherboard
architecture is being tested and adapted from the original LArg design to the TileCal needs at Valencia
Laboratory. This requires some hardware
modifications, basically related to different input optical links clocks
and protocol. The changes require the development of the firmware
for several complex programmable logic devices (FPGAs), the writting
of host software VME libraries
and reprogramming the whole FPGAs in the Processing
Units and their Digital Signal Processors (DSPs) to implement
the
TileCal online event reconstruction (e.g. optimal
filtering algorithms). There is a document (pdf, J.Castelo) explaining the specific requeriments to use the LAr
RoD for Tile calorimeter.
Developments
The ROD
demonstrator board was installed in the Summer 2003 testbeam.
It used for the first
time, online algorithms (optimal
and flat filtering) and the data was sucessfully taken and analyzed
offline. At present (Jan
2004)
the
group is involved
in
several
tasks
to
get
the
ROD
system
ready
for
testing
in
the Commissioning
Set-up, just before the next step which is the
ATLAS
Combined Testbeam. These tasks
are:
-
To build a C++ library (rod_final.so)
as a CMT package to control and configure the ROD VME
motherboard and its components (PUs and FPGAs), the TBM
and all the ROD crate modules. The library is based
in a ROD_crate class which contains a ROD class with several
nested
classes for the ROD components (OC class, Staging class,
PU class, etc.). The VME layer is implemented with the C++
wrapper of the
software ROD
Crate DAQ over the "vme_rcc" package (package "RCDVme"
of the ATLAS Dataflow repository).
The use of the ATLAS standard "RCDVme"
will allow the Online
Software integrators to do the job easily and faster.
-
To build two GUI based X-Window applications
called XTR and XFILAR to control the ROD crate modules and the FILAR module
respectively. This will allow to test our
system in a straightforward way avoiding extra high level software
layers and to have a user-friendly
interface provided by the X-Window.
Hardware availability:
Description
|
# |
Crate 9U ATLAS air cooled
|
2 |
| 9U ROD final motherboard with 8 integrated g-link inputs@40MHz |
2 |
| TTCvi |
1 |
| TTCvx |
1 |
| TTCpr |
1 |
| SBC VP110 ATLAS standard |
1 |
| FILAR s-link(HOLA) to PCI64 interface card |
1 |
| HOLA LSC s-link cards |
4 |
| Interface link CARD |
2 |
| ROD Injector holding 2 Interface Cards |
1 |
| Processing Unit dual DSPC6414@720MHz |
4 |
| Transition Module final ROD motherboard |
2 |
| VME Bus Monitor VBT-325 |
1 |
| 64 bits PCI computer for using with FILAR and S32PCI64 |
2 |
| CP3 custom backplane |
1 |
| 9U TBM (trigger and busy module) |
1 |
Test Benches
Several short and long term ROD functional tests
are foreseen. First is the use of the ROD
injector board at the lab. At a later stage RODs will be tested in a real physics
data and TileCal integrated environment, the "commissioning
set-up". In May 2004 the Combined
Testbeam will allow to test the TileCal RODs together with the whole ATLAS data acquisition integration.
This page is under construction and the results
of these tests will be put here as soon as available.
Documentation
The documentation for Tilecal RoD is beign prepared in parallel with hardware, firmware and software developments. By now, you can get a preliminary documentation browsing the "LAr RoD Final Design Review (FDR) (www agenda) (EDMS document)" and the tilecal document "TileCal ROD HW specific Requirements for using New LArg motherboard (J.Castelo)".
Links
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