CRC Page

In the next table is shown the input data format comming from the Tilecal FEB boards inside the drawers, the so called Interface Links. The ROD should provide an interface based on HDMP1032/HDMP10xx (xx= 24 or 34) for receiving all this data packets and check to flag errors when they occur. The table is for seven samples and It's easy to understand the changes when upgrading to another number of samples (e.g. in testbeam 9 where used).

Word nb.	Data word
1	START Control word ( 0x51115110 )
2	Header from DMU1
3	Data word , high/low gain sample 1 from DMU1
4	Data word , high/low gain sample 2 from DMU1
5	Data word , high/low gain sample 3 from DMU1
6	Data word , high/low gain sample 4 from DMU1
7	Data word , high/low gain sample 5 from DMU1
8	Data word , high/low gain sample 6 from DMU1
9	Data word , high/low gain sample 7 from DMU1
10	CRC word from DMU1
11	Header from DMU2
12	Data word , high/low gain sample 1 from DMU2
13	Data word , high/low gain sample 2 from DMU2
14	Data word , high/low gain sample 3 from DMU2
15	Data word , high/low gain sample 4 from DMU2
16	Data word , high/low gain sample 5 from DMU2
17	Data word , high/low gain sample 6 from DMU2
18	Data word , high/low gain sample 7 from DMU2
19	CRC word from DMU2
……	……………………………………….
138	Header from DMU16
139	Data word , high/low gain sample 1 from DMU16
140	Data word , high/low gain sample 2 from DMU16
141	Data word , high/low gain sample 3 from DMU16
142	Data word , high/low gain sample 4 from DMU16
143	Data word , high/low gain sample 5 from DMU16
144	Data word , high/low gain sample 6 from DMU16
145	Data word , high/low gain sample 7 from DMU16
146	CRC word from DMU16
147	CRC from DIGITIZER
148	Final Link CRC16 (CRC16 of entire block in 16bits words)
149	END Control word ( 0xFFFFFFF0 )

Table 1: Input data format

The data word has 32 bits and are aligned as shown in the Table 2 . Each fragment contains the data for three PMT channels and a bit of odd parity calculated for all 32 bits.

MSB					LSB
0	P	Data channel 1 (10 bits)	Data channel 2 (10 bits)	Data channel 3 (10 bits)

Table 2: Three channels data format (32bits)

Header format is represented in Table 3.

MSB

LSB

1

p

llll

e

s

d

r

vvvv

0

mm

ggg

bbbbbbbbbbbb

Table 3: fragment header format

The header starts with bit 31 set to indicate a header. The other bits are as follows:

p	Parity (odd)
l	Derandomizer length (number of samples. Up to 16).
e	Parity error . A parity error was detected from the memory in the last readout.
s	SEstr Single Error Strobe received from the ttc.
d	DEstr Double Error Strobe received from the ttc.
r	Register parity . Parity from the registers in the chip.
v	Variable parity . Parity from the variables in the chip.
0	Not used . (Set to 0)
m	Mode .	00 - Normal mode 01 - Calibration mode 10 - Test mode 11 - Not used
g	High/low gain . Indicates high(1) or low(0) amplification from the 3-in-1 cards.
b	Bunch Crossing .

 

CRC Calcs

There are 2 kind of CRCs checksums calculated over the data, one is CRC-CCITT16 and the other one is a normal CRC of 16 bits. A simple program for calculate CRC-CCITT16, CRC16, parity, header and trailer errors over a binary dump acquired is given (ROB_read_dat_check_raw_data.c).

• CRC-CCITT16:

The "Final Link CRC16" is calculated over the full event fragement not taking into account the header and trailer words (0x511151110 and 0xFFFFFFF0). This is generated by the APEX FPGA inside the Interface Link and it's coded in VHDL.

This CRC-CCITT16 uses the next configuration:

Width	16 bit
Poly	1021 This is the divisor polynome
Init	FFFF This is the initial value of the register
Refin	Output CRC is NOT reflected
Refout	Yes Reflect the checksum output
Xorout	No XOR is performed on the output CRC
check	29B1 This is the checksum for the ascii string "123456789"

Table 4: CRC-CCITT16

With ROD demostrator motherboard we decode the CRC using a vhdl code implementation in the double ODIN LDC installed in the transition module TM4Plus1 (VHDL).

The data acquired with RODdemo in summer 2003 testbeam was stored in binary dumps which contains Optimal Filtering and Flat Filtering reconstruction, and also raw data.

A test program for checking CRC-CCITT coded in C for testing this data is tile_crc_check.c.

More information about CRC-CITT could be found in References.

• CRC16:
  
  This a 16 bits CRC calculated over each DMU samples packet (see Table 1). This CRC (and the data) is sent from digitizers ASIC chip TileDMU (see the vhdl code of crc16) and checked and re-calculated in the interface links that reads up to 16 DMUs (vhdl)and sends the data with the data format shown in table 1.

  This CRC16 uses the next configuration:

Width	16 bit
Poly	8005 This is the divisor polynome
Init	0000 This is the initial value of the register
Refin	Yes Reflect the input e.g. bit 0 first
Refout	Yes Reflect the checksum output
Xorout	0000 Do not xor the checksum with anything
check	BB3D This is the checksum for the ascii string "123456789"

Table 5: CRC16

The CRC16 is calulated over the serialization of the data (32bits => 2 bit streams of 16 bits) according to the data format implemented in tiledmu:

31	32	Data, high gain, sample 4, bit 31 & 32    (last readout bits)
...	...	etc.
1	2	Data, high gain, sample 4, bit 1 & 2
...	...	etc.
		Data, high gain, sample 3
...	...	etc.
		Data, high gain, sample 2
...	...	etc.
1	2	Data, high gain, sample 1, bit 1 & 2
31	32	Header 2, bit 31 & 32
...	...	etc.
1	2	Header 2, bit 1 & 2
31	32	Data, low gain, sample 4, bit 31 & 32
...	...	etc.
1	2	Data, low gain, sample 4, bit 1 & 2
...	...	etc.
		Data, low gain, sample 3
...	...	etc.
		Data, low gain, sample 2
31	32	Data, low gain, sample 1, bit 31 & 32
...	...	etc.
3	4	Data, low gain, sample 1, bit 3 & 4
1	2	Data, low gain, sample 1, bit 1 & 2
31	32	Header 1, bit 31 & 32
...	...	etc.
5	6	Header 1, bit 5 & 6
3	4	Header 1, bit 3 & 4
1	2	Header 1, bit 1 & 2              (first readout bits)

Table 6: Data serialization in tileDMU

The Sample Program tile_crc_check.c also checks parity and calculates the CRC16 over an event fragment. Previously it serializes the data and then evaluates two crc16 words (crca, crcb). The crca upper word bit 32 is masked to zero because it is a data words (se 31 bit to zero in table 2.)

References

The following web page contains a javascript calculator that is handy for what-if comparisions in calculating various CRCs by slightly different methods and with any initial value, also a VHDL generation tool is given:

• http://rcswww.urz.tu-dresden.de/~sr21/crc.html -- CRC calculation, by Sven Reifegerste.
• http://www.easics.be/webtools/crctool -- CRC tool for code VHDL generation.

The following web pages were among those which were helpful in developing this document: