Technologies In this final section, some technology options for the forward region of the tracker are discussed. Clearly, the ILC detector R&D is a fast-moving field, and will hopefully present a few more surprises before the final technology decision is made. Therefore, the list here does not pretend to enter in much detail: it can at best aim to represent a broad overview of today's possibilities. Micro-strip detectors Today's state-of-the-art detectors in this established provide a cost-effective way of instrumenting large tracking volumes (the CMS detector contains 200 m2 of silicon micro-strip detector). These detectors provide an essentially one-dimensional measurement with very good precision. Typical LHC detectors with a pitch of 80 &mu m yield 23 &mu m resolution with binary read-out, up to a factor two better with analog read-out. Smaller strip pitches are very well possible, but for collider applications read-out pitches below 50 &mu m are not very common. The second coordenate is only very loosely constrained by the length of the strip, typically of the order of 5-20 cm. The area per read-out channel is relatively large: for 50 &mu m × 10 cm strips a single channeld corresponds to 5 mm 2 of the silicon area. This limits the application of the technology to areas of the detector where the track densities are less severe. The material budget is a sum of several components. To achieve a good S/N ratio, the active silicon wafer itself has a minimum thickness of 200 &mu m, amounting to a mere 2 &permil X0 (a radiation length in silicon is 9.4 cm). For all detectors built till today hybrid containing the read-out chips contributes significantly. In particular for the LHC detectors, the power density of the electronics leads to a signficant contribution of cables (to bring the power in) and cooling (to get it back out). At present, it has not been demonstrated that for the ILC applications, where radiation damage is much less of an issue, liquid cooling is required. But, neither has it been demonstrated that gas cooling is sufficient. This leaves considerable uncertainty as to the the effective contribution to the material of this type of technology. The current best guess for ILC silicon micro-strip detectors is 0.5 - 0.8 % X0/layer. Double-sided micro-strip detectors These detectors provide a two-dimensional measurement by combining the read-out of two micro-strips at an angle. For true double-sided detectors a single wafer is segmented on both sides (one side collecting the electron signal and the other the signal from holes). False double-sided detectors achieve a 2D measurement by mounting two single-sided micro-strip detectors back-to-back. The resolution of the primary and secondary coordenates depends on the read-out pitch and on the stereo-angle: the overlap between strips describes a rhomb with sides of p/sin( &alpha) and p/cos( &alpha) respectively. Double-sided detectors with perpendicular strips yield identical (and small) errors for both coordenates. However, these detector have the disadvantage of producing N2-N "ghost" measurements when N tracks incide on the detector. Therefore, their use is limited to applications where track density is not an issue. The LHC experiments employ stereo-angles of 40 mrad (ATLAS) and 100 mrad (CMS). This yields robust hit combinations (ghost hits only occur if two tracks are within a few mm of each other). There is strong hierarchy between the resolution of primary (close to &sigma/ &sqrt(2), i.e. 10-20 &mu m) and secondary coordenates ( &sigma / tan( &alpha ), i.e. of the order of several 100s of microns to a mm). The contribution to the overall budget of the active material for true double-sided detectors is similar to that of single-sided detectors. However, the channel density increases by a factor two; all components that scale with power are doubled. For false double-sided technology, all components of the material budget including the sensor material are doubled. Therefore, it is likely that double-sided detectors will end up towards the high end of the plausible 0.5 - 0.8 % X0 range, especially for the false double-sided options, where 4.3 &permil X0 is consumed up by the active material. Hybrid pixel detectors Hybrid silicon pixel detectors have become an established technology in the last decade. The active material is segmented in small square or rectangular pixels. Each pixel is read-out by a separate channel. To this end, the ead-out chips are mounted on top of the sensor wafer and all channels are connected by bump-bonds to the pixels. The LHC experiments have built relatively large (10s of millions of channels) vertex detectors in this technology. The pixel size ranges from 150 × 150 &mu m2 (CMS) to 50 × 500 &mu m2. The best achievable space point resolution is of the order of 10 &mu m. Beyond 50 &mu m × 50 &mu m, only marginal reduction of the pixel size is expected in the next decade. The weakness of this technology is the material budget. The active material cannot be reduced much beyond 200 &mu m. Typical thinned read-out chips contribute about the same amount. Therefore, the bare minimum contribution to the material budget (ignoring support structures, cables and cooling) is 4.3 &permil X0. The experience in the LHC indicates that the actual material in the detectors+services as built may be far beyond that. The channel density and the consequent power consumption (several 10s of kW for ATLAS, CMS, several kW for the BTeV pixel detectors) require liquid cooling and massive power cables. The ATLAS and CMS detector as built contribute 3 - 13 % X0/measurement (the barrel+end-cap geometry guarantees three measurement points) depending on the region of the detector. The comparison with the ILC is admittedly not fair. The possibility of power cycling and operation of the sensors at more moderate temperatures should render the ILC constraints much less severe. However, it is unlikely that a detector can be built in this technology within a material budget of less than 1 % X0. Active pixel detectors The next generation of pixel detectors uses so-called active pixel sensors. In this case, (part of) the amplification and read-out functionality that was traditionally taken care of by the read-out chip, is moved into the sensor. Several technologies are being developed. Some (MAPs, DEPFETs) have developed into working prototypes. The performance of such detectors is a step beyond what was achievable with hybrid detector technology. Pixel sizes of 25 × 25 &mu m 2 have been achieved. The envisaged resolution of these technologies in the ILC vertex detector is better than 5 &mu m. Perhaps an even larger gain is achieved in the power consumption and material budget. Due to the very low noise, the sensor thickness can be reduced to 50 &mu m maintaining an adequate S/N ratio. Thus, it is hoped that in the ILC vertex detector each layer contributes only 1 &permil X0 to the overall budget. The power consumption - accounting for power cycling in the period between bunch trains - could be kept extremely low, down to the order of 10 W for the entire, 5-layer vertex detector. The mechanical stability of such thin detector layers clearly is an issue to be resolved. Home Next Article