ROD-Software sources reference
At the Valencia ROD Lab, one of the the main tasks is to install a
SLink
SetUp environment where the ROD links And Aritmethic issues over the
front end data can be evaluated and designed.
The approach mix hardware and software items to have a clear
status of the technologies involved in the ROD performance.
A PC running LINUX and equipped
with a PCI/Slink
board simulate the LVL1 flow data obtained from either TestBeam Data or Montecarlo simulations. Other two PCI boards, PCI/SCI, and
Bit3-PCI
provide two extra links to access to the VME ROD crate or directly to the ROD
module. Another PC-Linux Server provides the LynxOS kernels and the remote root file systems to the VME CPU hosts (PowerPC and MVME167) using the local network and the BOOTP and tftp protocols.
Motorola
2604 PowerPC + PMCSpan
will be our ROD CPU where TileCal algorithms and functionalities will be
tested.
PMCSpan is a daughter board which provides since two PMC Sites expanding the
PCI local bus of the PPC motherboard.
This environment is easily transported, in terms of software and hardware
to the TestBeam, which usually use the RD13 DAQ system.
The
first media technology to be evaluated as physical layer of SLINK has been
Fiberchannel. On
June-July 98 Testbeam period,
Front End data has been read out using a
LDC
(Fiberchannel-Slink v2.0) ;commercial board, a
PowerPC-RIO2
running
LynxOS
which allocates a
S-Link to PMC
board where the LDC daughter board is plugged.
The arithmetic Algorithms will run in the PowerPC under LynxOS.
A C software code design of such tasks is the natural approach.
Inside this environment, DSPs or custom FPGAs based on PMCs format
can be easily evaluated as ATLAS ROD processors such as the TileCal
work document plans.
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TileCal ROD
Maintaned by Juanba Ific, University of Valencia |
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