Motorola 2604 PowerPC + PMCSpan will be our ROD CPU where TileCal algorithms and functionalities will be tested. PMCSpan is a daughter board which provides since two PMC Sites expanding the PCI local bus of the PPC motherboard. This environment is easily transported, in terms of software and hardware to the TestBeam, which usually use the RD13 DAQ system.
The first media technology to be evaluated as physical layer of SLINK has been Fiberchannel. On June-July 98 Testbeam period, Front End data has been read out using a LDC (Fiberchannel-Slink v2.0) ;commercial board, a PowerPC-RIO2 running LynxOS which allocates a S-Link to PMC board where the LDC daughter board is plugged.
The arithmetic Algorithms will run in the PowerPC under LynxOS. A C software code design of such tasks is the natural approach. Inside this environment, DSPs or custom FPGAs based on PMCs format can be easily evaluated as ATLAS ROD processors such as the TileCal work document plans.
TileCal ROD
Maintaned by Juanba Ific, University of Valencia |